A clock synchronization circuit is known that outputs a clock signal in synchronization with an input clock signal. For example, a clock synchronization circuit is known that includes a frequency divider to perform frequency-divide operation with a certain frequency dividing ratio that may be changed for an input auxiliary clock signal, a phase synchronization loop circuit that operates based on a frequency-division clock signal that is output from the frequency divider, and a frequency dividing ratio control unit to which a certain reference clock signal is input and determines a frequency dividing ratio of a frequency divider to a certain fixed value when a phase difference between a reference clock signal and a frequency division clock signal is within a certain range (for example, refer to Japanese Laid-open Patent Publication No. 2000-31819).
A PLL circuit is known that includes a VCXO oscillator circuit, a first frequency-dividing circuit that receives an output of the VCXO oscillator circuit, a second frequency-dividing circuit that receives a reference clock from an external source, a phase comparator circuit that receives an output of the first frequency-dividing circuit and the second frequency-dividing circuit, and a filter circuit that receives an output of the phase comparator circuit and outputs a certain control voltage for the VCXO oscillator circuit.
The PLL circuit may include, for example, a gate circuit that operates as required at an input stage of the first frequency-dividing circuit, a sample/hold circuit provided between the filter circuit and the VCXO oscillator circuit, a clock interruption detection circuit that detects an interrupted state immediately when a reference clock received from the external source is interrupted, and a control circuit that controls driving of the gate circuit and the sample/hold circuit according to an output signal from the clock interruption detection circuit (for example, Japanese Laid-open Patent Publication No. 05-129948)